A typical critical path in microprocessor designs is through the logic which generates the effective address (EA) for a load instruction (an adder) and then decodes that address to access the data cache (word line decoder). For load instructions and store instructions it is very important to "speed up" the processing of such instructions because they can take up to 40-50 percent of the instructions encountered in the execution of typical code by a microprocessor. In order to access a cache, an effective address (EA) is generated and must be followed by a word-line decoder to provide the output.
Accordingly, it is very important to speed up the access of the cache. As is well known, this is generally important to ensure that the instruction per cycle is optimized for each device. The latency associated with the critical path is also of paramount importance to the performance of the processor because load instructions are common and their latency determines when dependent instructions can start executing (i.e., the path cannot be split into multiple cycles without incurring a performance penalty).
Accordingly, what is needed is an improved logic circuit for providing a faster generation of the EA. The system should be simple and cost effective. In addition the system should be easily implemented in existing processor designs. The present invention addresses such a need.